1. Field of the Invention
The present invention relates to a clock generation circuit and a semiconductor device including the same, and more particularly to a clock generation circuit having a duty adjustment circuit and a semiconductor device including the same. The present invention also relates to a method of generating a clock signal, and more particularly to a method of generating a clock signal with a duty adjustment.
2. Description of Related Art
In recent years, synchronous memories which operate in synchronization with a clock signal have been widely used for main memories of personal computers and the like. DDR (Double Data Rate) synchronous memories absolutely need a DLL circuit for generating an internal clock signal synchronous with an external clock signal since the input and output data needs to be exactly synchronized with the external clock signal.
The DLL circuit generates the internal clock signal by delaying the external clock signal. The amount of delay is determined by comparing the phase of the rise edge of the external clock signal with that of the rise edge of the internal clock signal (replica clock signal) which has the same phase as that of read data. Specifically, if the rise edge of the internal clock signal lags behind the rise edge of the external clock signal in phase, the DLL circuit decreases the amount of delay for phase matching. On the other hand, if the rise edge of the internal clock signal leads the rise edge of the external clock signal in phase, the DLL circuit increases the amount of delay for phase matching.
The internal clock signal desirably has a duty of 50%. The fall edge of the internal clock signal is thus typically adjusted by using a duty adjustment circuit (DCC). A typical duty adjustment circuit alternately discharges two capacitors by using in-phase and reversed phase signals of the internal clock signal, and compares the potentials of the discharged capacitors to determine the duty. If the duty is determined to be above 50%, the fall edge of the internal clock signal is advanced to decrease the duty. If the duty is determined to be below 50%, the fall edge of the internal clock signal is delayed to increase the duty.
The foregoing duty adjustment circuit has had the problem that it is only applicable to a narrow frequency range since the amounts of discharge vary largely depending on the frequency of the internal clock signal. Specifically, if the internal clock signal is low in frequency (the internal clock signal has long cycles), the amounts of discharge can be so large that the capacitor potentials are saturated to make the duty detection not possible. On the other hand, if the internal clock signal is high in frequency (the internal clock signal has short cycles), the amounts of discharge can be so small that the resulting potential difference shrinks to cause a misjudgment.
Such a problem can be solved, for example, by a DLL circuit that is described in Japanese Patent Application Laid-Open No. 2005-218091. The DLL circuit described in Japanese Patent Application Laid-Open No. 2005-218091 is a type of DLL circuit that uses oscillators to adjust the positions of the rise and fall edges of the internal clock signal. Since there is no need to discharge capacitors as in the foregoing duty adjustment circuit, the foregoing problem can be solved. Unlike typical DLL circuits, a delay line for delaying the external clock signal is also unnecessary.
Other known examples of the circuit for generating an internal clock signal include the circuits described in Japanese Patent Application Laid-Open Nos. 2004-129255, 2007-097182, and 2008-311999.
However, the DLL circuit described in Japanese Patent Application Laid-Open No. 2005-218091 needs a plurality of oscillators, and thus has had the problem that the oscillators can serve as noise sources. There has been another problem that no use of a delay line, unlike typical DLL circuits, precludes simple application of the DLL circuit technologies that have been accumulated so far. Under the circumstances, it is desired for a typical DLL circuit using a delay line to implement an improved duty adjustment circuit that is independent of the clock signal frequency.